1. Field of the Invention
The invention relates to an output apparatus, an output driver and a level shifting system.
2. Description of the Related Art
An integrated circuit is generally divided into a core portion and an input/output (I/O) portion. The I/O portion bridges the communication to the external for the core portion. In addition to transmitting core signals generated by the core portion to outside the integrated circuit via a pad, the I/O portion also needs to transmit external signals sent from the external to the pad further to the core portion for processing.
It is required that the operating voltage of the core portion be reduced with demands of the increasing operating speed and power saving effect of electronic products. Similarly, to increase the transmission efficiency of external signals between integrated circuits, the driving voltage of new-generation external signals is also lowered. Take a double-data-rate three synchronous dynamic random access memory (DDR3 SDRAM) for example. The specified operating voltage of the DDR3 SDRAM is 1.5V, whereas the operating voltages of the DDR1 and DDR2 SDRAMs are 2.5V and 1.8V, respectively. In the latest DDR4, the operating voltage is reduced to even as low as 1.2V.
Two devices can be manufactured from a semiconductor wafer by a conventional semiconductor manufacturing process—a core device and an I/O device. For example, it is essential that the reliability of the core device be ensured under all kinds of operating voltage combinations when all conducting nodes (e.g., the gate, drain and source) operate under a 1.1V voltage. Further, it is essential that the reliability of the I/O device be ensured under all kinds of operating voltage combinations when all conducting nodes (e.g., the gate, drain and source) operate under a 1.5V voltage. For example, when the I/O device and the core device are both MOS devices, the gate oxidation layer in the I/O device is thicker than the gate oxidation layer in the core device. In comparison, the core device has a faster speed and a larger driving capability, while the I/O device has better robustness for withstanding a higher voltage stress.
FIG. 1 shows a conventional output apparatus 100, which is applicable to DDR3 and is an I/O portion in an integrated circuit. The output apparatus 100 drives a pad 102, and is powered by power lines Vddio and Vssio having 1.5V and 0V voltages, respectively. The output apparatus 100 includes a level shifting circuit 106, a high buffer circuit 108H, a low buffer circuit 108L, and an output driver 110. For speed and power-saving considerations, a core circuit 104 adopts a core device, and is powered by core power lines Vddcore and Vsscore having 1.1V and 0V voltages, respectively. The output apparatus 100 adopts an I/O device. In the output driver 100, implemented by I/O devices with smaller driving capabilities and being required to satisfy DDR3 driving capability specifications, a pull-up PMOS PH and a pull-down NMOS NL occupy a considerable amount of a silicon area.
In the prior art, it is proposed that a core device be utilized in the conventional output driver to reduce the silicon area required. FIG. 2 shows another conventional output driver 120 for replacing the output driver 110 in FIG. 1. In the output driver 120, PMOS PH1 and PH2 as well as NMOS NL1 and NL2 are implemented by core devices. Control gates of the PMOS PH2 and the NMOS NL2 are respectively connected to power lines Vbp and Vbn having 0.4V and 1.1V voltages, respectively. A control gate of the PMOS PH1 receives a logic signal Sp, whose high and low logic levels are 1.5V and 0.4V, respectively. A control gate of the NMOS NL1 receives a logic signal Sn, whose high and low logic levels are 1.1V and 0V, respectively. The high logic level refers to a voltage level of a signal when the signal is logic “1”, and the low logic level refers to the voltage of the signal when the signal is logic “0”. The PMOS PH1 and PH2 are connected in series, and the NMOS NL1 and NL2 are connected in series. Such series structure prevents the core devices (the PMOS PH1 and PH2 as well as the NMOS NL1 and NL2) originally operating at a 1.1V operating voltage from potential damages caused by the stress of an excessive operating voltage (1.5V).
In the output driver 120, parasitic capacitance between the control gate of the PMOS PH2 and the pad 102 is quite large. To prevent capacitance coupling from causing an unstable voltage of the power line Vpb when a signal change occurs at the pad 102, the control gate of the PMOS PH2 needs to be connected to a large decoupling capacitor 122. Similarly, the control gate of the NMOS NL2 also needs to be connected to a large decoupling capacitor 124 to mitigate influences that the signal change at the pad 102 poses on the voltage of the power line Vbn. The decoupling capacitors 122 and 124 also occupy a considerable amount of the silicon area.